Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same
US7087947B2 · kind B2 · utility
2Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Oct 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.