System of multiplexed data lines in a dynamic random access memory
US7088624B2 · kind B2 · utility
30Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2003 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Nov 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system of multiplexed data lines in a DRAM integrated circuit includes a switching circuit having two switching states. In one switching state, the data lines connect to a first configuration of data paths as would occur in a typical DRAM integrated circuit. A limited number of spare column select lines are available to repair defective column select lines in the first configuration. In another switching state, the data lines connect to a second configuration of the data paths, doubling the number of spare column select lines available to repair a defective column select line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.