Reducing memory access latencies from a bus using pre-fetching and caching
US7089367B1 · kind B1 · utility
8Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1999 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Apr 10, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99955
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and apparatus to reduce latency in accessing a memory from a bus. The apparatus comprises a pre-fetcher and a cache controller. The pre-fetcher pre-fetches a plurality of data from the memory to a cache queue in response to a request. The cache controller is coupled to the cache queue and the pre-fetcher to deliver the pre-fetched data from the cache queue to the bus in a pipeline chain independently of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.