Multiple clock domain microprocessor
US7089443B2 · kind B2 · utility
21Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2004 |
| Grant date | Aug 8, 2006 |
| Priority date | — |
| Expiry date | Jul 5, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.