Wafer level packages for chips with sawn edge protection
US7091062B2 · kind B2 · utility
45Cited by
7References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 15, 2004 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Oct 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a wafer level package for chips with chip edge protection, comprising individual chips, which can in each case be mounted on a suitable carrier board, and to a method for producing such a wafer level package. Aspects of the invention can be achieved by the chip being thinned extremely from the back side and bonded onto a fiber reinforced synthetic resin sheet, forming a solidly bonded assembly that cannot come apart in the customary temperature range, and the edges of the assembly being at least partly coated with a polymer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.