Three dimensional integrated circuits
US7091604B2 · kind B2 · utility
21Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2004 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Aug 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional integrated circuit that provides reduced interconnect signal delay over known 2-dimensional systems. The three-dimensional integrated circuit also allows improved circuit cooling. The three-dimensional integrated circuit includes two or more electrically connected integrated circuits, separated by a cooling channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.