Data acknowledgment using impedance mismatching
US7091743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2003 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Oct 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4269
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.