Series feram cell array
US7092276B2 · kind B2 · utility
1Cited by
10References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2005 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Jan 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.