Method and apparatus for coherent memory structure of heterogeneous processor systems
US7093080B2 · kind B2 · utility
15Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2003 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Oct 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.