Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
US7093206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2003 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | May 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.