Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices
US7093208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2004 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Oct 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.