Noise analysis for an integrated circuit model
US7093223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Aug 15, 2006 |
| Priority date | — |
| Expiry date | Apr 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.