Semiconductor device with reduced memory leakage current
US7095074B2 · kind B2 · utility
5Cited by
4References
64Claims
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Key dates
| Filing date | Jul 17, 2002 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Feb 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/48
Abstract
Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.