Electrically-alterable non-volatile memory cell
US7095076B1 · kind B1 · utility
14Cited by
53References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2004 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Jul 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.