Narbeh Derhacobian
57Patents
24h-index
45Co-inventors
88Inventor score
Filing activity: Aug 19, 1997 → Aug 31, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5991202A | Method for reducing program disturb during self-boosting in a NAND flash memory | Physics | 204 | Expired |
| US6215702A | Method of maintaining constant erasing speeds for non-volatile memory cells | Physics | 165 | Expired |
| US6269023A | Method of programming a non-volatile memory cell using a current limiter | Physics | 139 | Expired |
| US6541816B2 | Planar structure for non-volatile memory devices | Emerging Cross-Sectional Technologies | 83 | Expired |
| US6567303B1 | Charge injection | Physics | 76 | Expired |
| US6442074B1 | Tailored erase method using higher program VT and higher negative gate erase | Physics | 73 | Expired |
| US6618290B1 | Method of programming a non-volatile memory cell using a baking process | Physics | 70 | Expired |
| US6590811B1 | Higher program VT and faster programming rates based on improved erase methods | Physics | 68 | Expired |
| US6307784A | Negative gate erase | Electricity | 62 | Expired |
| US6788574B1 | Electrically-alterable non-volatile memory cell | Electricity | 60 | Expired |
| US6468865B1 | Method of simultaneous formation of bitline isolation and periphery oxide | Electricity | 53 | Expired |
| US6456533B1 | Higher program VT and faster programming rates based on improved erase methods | Physics | 50 | Expired |
| US6529410B1 | NAND array structure and method with buried layer | Electricity | 49 | Expired |
| US6555436B2 | Simultaneous formation of charge storage and bitline to wordline isolation | Emerging Cross-Sectional Technologies | 44 | Expired |
| US6456536B1 | Method of programming a non-volatile memory cell using a substrate bias | Physics | 43 | Expired |
| US6514830B1 | Method of manufacturing high voltage transistor with modified field implant mask | Electricity | 41 | Expired |
| US6519182B1 | Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure | Physics | 41 | Expired |
| US8331128B1 | Reconfigurable memory arrays having programmable impedance elements and corresponding methods | Physics | 40 | Active |
| US6327183A | Nonlinear stepped programming voltage | Physics | 39 | Expired |
| US6356482B1 | Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure | Physics | 31 | Expired |
| US6465306B1 | Simultaneous formation of charge storage and bitline to wordline isolation | Emerging Cross-Sectional Technologies | 30 | Expired |
| US6246610A | Symmetrical program and erase scheme to improve erase time degradation in NAND devices | Physics | 30 | Expired |
| US6143608A | Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation | Electricity | 25 | Expired |
| US8687403B1 | Circuits having programmable impedance elements | Physics | 24 | Active |
| US6159795A | Low voltage junction and high voltage junction optimization for flash memory | Emerging Cross-Sectional Technologies | 23 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.