Variable impedance output buffer
US7095246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2004 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Oct 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.