PVT-compensated clock distribution
US7095265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2005 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Apr 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00143
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the clock buffers in response to process, voltage, and temperature variations, and consequently maintains a relatively constant signal-propagation delay through the network. In one embodiment, each clock buffer includes skew-offset circuitry that adds to or subtracts from the PVT compensated delay values provided by the PVT control circuit to simplify clock skew minimization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.