A/D converter with minimized transfer error
US7095346B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2004 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Apr 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An A/D converter has at least one converter stage which, respectively, has a sample and hold circuit for sampling an analog input signal. The converter stage also includes a comparator unit that compares the analog input signal with a reference value in order to produce a digital output value from the converter stage, a digital/analog converter for converting the digital output value into an analog signal, a subtractor for subtracting the analog signal from the sampled input signal, a signal amplifier for amplifying the output signal which is output by the subtractor with a particularl singal gain factor for the next converter stage, and a weighting unit for multiplying the digital output value by a multiplier for addition to further weighted output values from converter stages to produce the digital output value from the A/D converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.