On-chip high speed data interface
US7096290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Nov 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit can store data relating to a request to be sent, and the second circuit unit cannot store data relating to a received request. Thus, an on-chip interface is provided that may increase the overall system performance and that may support split transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.