Tracking the least frequently erased blocks in non-volatile memory systems
US7096313B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2002 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. According to one aspect of the present invention, one method for processing elements included in a non-volatile memory of a memory system includes obtaining erase counts associated with elements and grouping a number of the elements into a first set. Each element has an associated erase count that substantially indicates a number of times the element has been erased. Grouping the number of elements into the first set includes selecting elements included in the plurality of elements which have the lowest associated erase counts of the erase counts associated with the plurality of elements. The method also includes storing the erase counts associated with the first set in a memory component substantially within a table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.