Memory controller for multilevel cell memory
US7096406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2002 |
| Grant date | Aug 22, 2006 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.