Semiconductor device including bit line formed using damascene technique and method of fabricating the same
US7098135B2 · kind B2 · utility
5Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Jun 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a bit line formed using a damascene technique and a method of fabricating the same. The method includes forming an insulating layer on a substrate, forming a groove by etching the insulating layer to a partial depth, and forming spacers on the inner walls of the groove. An opening is formed by etching the insulating layer disposed under the groove using the spacers as an etch mask. A conductive layer is formed to fill the opening. A capping layer is formed to fill the groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.