Layout patterns for deep well region to facilitate routing body-bias voltage
US7098512B1 · kind B1 · utility
18Cited by
9References
56Claims
0Family size
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Key dates
| Filing date | Oct 10, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Dec 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.