Electrical interconnect with minimal parasitic capacitance
US7098540B1 · kind B1 · utility
44Cited by
13References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Jul 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention discloses an electrical interconnect with minimal parasitic capacitance. In one embodiment, an apparatus comprises a semiconductor substrate, and first and second support structures formed on the substrate, where the second support structure at least partially surrounds the first support structure on the substrate. The first and second support structures are each configured to support an electrical connector to be formed over the first and second support structures on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.