Functional register decoding system for multiple plane operation
US7099226B2 · kind B2 · utility
5Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Dec 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.