Digital communications processor

US7100020B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Thomas B. Brightman · Niwot, US
• Andrew Brown · Houston, US
• John F. Brown · Calgary, CA
• James Arthur Farrell · Harvard, US
• Andrew D. Funk · Brooklyn, US
• David J. Husak · Windham, US
• Edward J. McLellan · Holliston, US
• Mark A. Sankey · Acton, US
• Paul Schmitt · Merrimack, US
• Donald A. Priore · Maynard, US

Key dates

• Filing date: May 7, 1999
• Grant date: Aug 29, 2006
• Expiry date: May 7, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L49/3036
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.