Hierarchical gcell method and mechanism
US7100129B1 · kind B1 · utility
11Cited by
14References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Mar 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.