Inventor · Monte Sereno, CA, US

Eric Nequist

37Patents
12h-index
17Co-inventors
78Inventor score

Filing activity: Jan 14, 2003 → Dec 27, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8717182B1 Mechanism and method to implement a reader mechanism for a container-based monitor of a consumable product Electricity 35 Active
US7096445B1 Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit Physics 33 Expired
US10672663B2 3D chip sharing power circuit Electricity 23 Active
US7100128B1 Zone tree method and mechanism Physics 23 Expired
US10586786B2 3D chip sharing clock interconnect layer Electricity 22 Active
US10580757B2 Face-to-face mounted IC dies with orthogonal top interconnect layers Electricity 22 Active
US7725845B1 System and method for layout optimization using model-based verification Emerging Cross-Sectional Technologies 22 Active
US6981235B1 Nearest neighbor mechanism Physics 20 Expired
US6983440B1 Shape abstraction mechanism Physics 17 Expired
US7461359B1 Method and mechanism for determining shape connectivity Physics 15 Active
US7516433B1 Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit Physics 15 Active
US7657860B1 Method and system for implementing routing refinement and timing convergence Physics 13 Active
US7100129B1 Hierarchical gcell method and mechanism Physics 11 Expired
US7861203B2 Method and system for model-based routing of an integrated circuit Physics 10 Active
US7721235B1 Method and system for implementing edge optimization on an integrated circuit design Emerging Cross-Sectional Technologies 8 Active
US7614028B1 Representation, configuration, and reconfiguration of routing method and system Physics 7 Active
US7665045B1 Method and mechanism for identifying and tracking shape connectivity Physics 7 Expired
US7590955B1 Method and system for implementing layout, placement, and routing with merged shapes Emerging Cross-Sectional Technologies 6 Active
US7698666B2 Method and system for model-based design and layout of an integrated circuit Physics 5 Active
US8069426B2 Method and mechanism for identifying and tracking shape connectivity Physics 4 Active
US8010917B2 Method and system for implementing efficient locking to facilitate parallel processing of IC designs Physics 4 Active
US11557516B2 3D chip with shared clock distribution network Electricity 3 Active
US8136060B1 Method and mechanism for identifying and tracking shape connectivity Physics 3 Active
US7904862B2 Method and mechanism for performing clearance-based zoning Physics 3 Active
US7971173B1 Method and system for implementing partial reconfiguration and rip-up of routing Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.