System and method for topology selection to minimize leakage power during synthesis
US7100144B2 · kind B2 · utility
9Cited by
1References
34Claims
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Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Jul 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology and the leakage sensitivities for each of the topologies is calculated. The system is then configured to synthesize a new circuit model by selecting one or more of the topologies based on its leakage sensitivities, wherein the new circuit model has reduced current leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.