Method of forming ladder-type gate structure for four-terminal SOI semiconductor device
US7101745B2 · kind B2 · utility
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2References
7Claims
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Assignee
Inventor
Key dates
| Filing date | Dec 3, 2004 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Dec 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A ladder-type gate structure for a silicon-on-insulator (SOI) four-terminal semiconductor device is disclosed. The structure includes a gate having a first and second portion, a body region, which is under the first portion of the gate, a body contact, which is adjacent to the second portion of the gate, and a plurality of body contacts connecting the body region to the body contact through a drain region. The gate structure provides an independently controlled body region and includes a substantially uniform voltage across the body region in the SOI semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.