Paul A. Hyde
12Patents
4h-index
15Co-inventors
49Inventor score
Filing activity: Oct 31, 2003 → May 4, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7406397B2 | Self heating monitor for SiGe and SOI CMOS devices | Physics | 10 | Expired |
| US7862233B2 | Self heating monitor for SiGe and SOI CMOS devices | Physics | 9 | Active |
| US6861716B1 | Ladder-type gate structure for four-terminal SOI semiconductor device | Electricity | 5 | Expired |
| US8296691B2 | Methodology for improving device performance prediction from effects of active area corner rounding | Physics | 4 | Active |
| US8392867B2 | System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists | Physics | 4 | Active |
| US7805274B2 | Structure and methodology for characterizing device self-heating | Physics | 2 | Active |
| US8539426B2 | Method and system for extracting compact models for circuit simulation | Physics | 0 | Active |
| US8302040B2 | Compact model methodology for PC landing pad lithographic rounding impact on device performance | Physics | 0 | Active |
| US7818693B2 | Methodology for improving device performance prediction from effects of active area corner rounding | General | 0 | Revoked |
| US7979815B2 | Compact model methodology for PC landing pad lithographic rounding impact on device performance | Physics | 0 | Active |
| US8412487B2 | Self heating monitor for SiGe and SOI CMOS devices | Physics | 0 | Active |
| US7101745B2 | Method of forming ladder-type gate structure for four-terminal SOI semiconductor device | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.