Self-aligned double gate mosfet with separate gates
US7101762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2005 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Feb 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/674
Abstract
A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.