Self-aligned selective hemispherical grain deposition process and structure for enhanced capacitance trench capacitor
US7101768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Sep 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/665
Abstract
As disclosed herein, a method is provided, in an integrated circuit, for forming an enhanced capacitance trench capacitor. The method includes forming a trench in a semiconductor substrate and forming an isolation collar on a sidewall of the trench. The collar has at least an exposed layer of oxide and occupies only a “collar” portion of the sidewall, while a “capacitor” portion of the sidewall is free of the collar. A seeding layer is then selectively deposited on the capacitor portion of the sidewall. Then, hemispherical silicon grains are deposited on the seeding layer on the capacitor portion of the sidewall. A dielectric material is deposited, and then a conductor material, in that order, over the hemispherical silicon grains on the capacitor portion of the sidewall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.