Gate controlled floating well vertical MOSFET
US7102914B2 · kind B2 · utility
11Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Sep 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/211
Abstract
A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate overdrive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.