Circuit arrangement for latency regulation
US7102940B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2005 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Mar 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the invention relates to a circuit arrangement for regulating a latency that is defined as a whole number n of periods T of a reference clock of frequency fc and is intended to elapse, as of a data transmission command, before the data which are to be transmitted from a data source appear at the end of the data path that is to be passed through and contains a chain of transmission elements having fixed delay times. The frequency fc may be set in a range from 1/Tmax to 1/Tmin, where Tmin is at least equal to τf/n and τf is equal to the sum of the fixed delay times in the data path. The data path is subdivided into n successive sections, each of which contains, at its input, a clock-controlled sampling element for accepting the data to be transmitted and has a propagation time that is considerably shorter than Tmin. The propagation time τn of the last section (Sn) is considerably greater than zero. The clock of the sampling elements is controlled using a version of the reference clock that has been delayed by T−τn.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.