Shader cache using a coherency protocol
US7103720B1 · kind B1 · utility
18Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2003 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Sep 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for caching graphics data using dedicated level one caches and a shared level two cache are described. Furthermore, each method includes a protocol for maintaining coherency between the level one caches and between the level one caches and the level two cache. The level one caches may store different versions of the graphics data, permitting simultaneous processing of execution threads, each thread accessing a different version of the graphics data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.