Verification of embedded test structures in circuit designs
US7103860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2003 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Feb 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318307
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A program product for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor for parsing a verification specification containing test specifications for selected test structures and a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.