Routing scheme for differential pairs in flip chip substrates
US7105926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2003 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Jan 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip chip substrate is provided, which includes a plurality of conductive layers, including a top layer and a bottom layer. A first plurality of contacts, including first and second contacts corresponding to a differential signal pair, are arranged on the top layer within a die bonding area. A second plurality of contacts, including third and fourth contacts corresponding to the differential signal pair, are arranged on the bottom layer. First and second traces are routed between the first and third contacts and between the second and fourth contacts, respectively, wherein the second trace is routed out of the die bonding area on a different layer than the first trace. The traces are routed in a manner that reduces the length difference between the traces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.