Parallel calibration system for a test device
US7106081B2 · kind B2 · utility
6Cited by
14References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Aug 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R35/005
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.