Testing system and testing method for DUTs
US7106083B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Dec 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device characteristic testing system for testing a first DUT (device under test), a second DUT, a third DUT and a fourth DUT on a wafer, each of the DUTs includes a first end and a second end, the device characteristic testing system includes: a device characteristic testing circuit formed on the wafer includes a first conducting line connected to the second end of the first and the fourth DUT, a second conducting line connected to the second end of the second and third DUTs, a third conducting line connected to the first end of the first and second DUTs, a fourth conducting line connected to the first end of the third and fourth DUT, and a plurality of testing pads respectively coupled to the first, second, third, and fourth conducting line for receiving at least one testing signal to detect device characteristics of the DUTs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.