Multi-phase clock signal generator and method having inherently unlimited frequency capability
US7106655B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Feb 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The remaining delay lines are each composed of different numbers of variable delay units to provide respective clock signals having different phases, but they do not include any of the fixed delay units. The first and a last delay line receive an input clock signal. Each of the remaining delay lines are coupled to an output of one of the fixed delay units depending on the number of variable delay units in the delay line so that the resulting clock signals have all been delayed the same number of fixed delay periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.