Digital delay locked loop with extended phase capture range
US7107475B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2003 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Dec 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00241
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the input signal, and dependent on the comparison, the delay code is updated to indicate whether the delay array needs to provide more delay or less delay. The digital delay locked loop also uses a detection circuit that monitors for a predetermined condition of the delay code. In response to detection of the predetermined condition, the delay code is automatically reset to a value different than a value of the delay code present at a previous reset or initial startup of the digital delay locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.