Formation method for semiconductor layer
US7108745B2 · kind B2 · utility
0Cited by
3References
13Claims
0Family size
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Key dates
| Filing date | Apr 16, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Apr 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3245
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
After a Group III-V compound semiconductor layer, to which a p-type dopant has been introduced, has been formed over a substrate, the compound semiconductor layer is annealed. In the stage of heating the compound semiconductor layer, atoms, deactivating the p-type dopant, are eliminated from the compound semiconductor layer by creating a temperature gradient in the compound semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.