Method of manufacturing a superjunction device
US7109110B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/127
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.