Electrochemical fabrication methods including use of surface treatments to reduce overplating and/or planarization during formation of multi-layer three-dimensional structures
US7109118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | May 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating three-dimensional structures from a plurality of adhered layers of at least a first and a second material wherein the first material is a conductive material and wherein each of a plurality of layers includes treating a surface of a first material prior to deposition of the second material. The treatment of the surface of the first material either (1) decreases the susceptibility of deposition of the second material onto the surface of the first material or (2) eases or quickens the removal of any second material deposited on the treated surface of the first material. In some embodiments the treatment of the first surface includes forming a dielectric coating over the surface and the second material is electrodeposited (e.g. using an electroplating or electrophoretic process). In other embodiments the first material is coated with a conductive material that doesn't readily accept deposits of electroplated or electroless deposited materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.