Dual referenced microstrip
US7109569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Sep 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane. A method, according to one embodiment of the invention, includes the calculation of a first characteristic impedance of the dual referenced microstrip transmission line referenced to a primary reference layer, the calculation of a second characteristic impedance of the dual referenced microstrip transmission line referenced to a secondary reference layer, the calculation of an absolute value of a difference between the first and the second characteristic impedance, the comparison of the absolute value of the difference to a predetermined threshold value, and if the absolute value of the difference is greater than the predetermined threshold value, then a physical parameter associated with the characteristic impedance between the primary and secondary reference layers may be varied until the difference is reduced to less than the predetermined threshold. A structure, according to one embodiment of the invention includes a micros…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.