Integrated circuit package with leadframe enhancement and method of manufacturing the same
US7109570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Mar 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.