Generating different delay ratios for a strobe delay
US7109767B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Sep 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.