Method and apparatus for dual pass adaptive tessellation
US7109987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Dec 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.