Method and apparatus for reducing effect of jitter
US7110446B1 · kind B1 · utility
1Cited by
10References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Sep 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically processed to select a tap of another delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.